1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of forming a semiconductor device having a dielectric layer composed of an oxide, a nitride, and an oxide layer.
2. Description of Related Art
Semiconductor memory devices generally are characterized as volatile memory devices, such as DRAM (dynamic random access memory) and SRAM (static random access memory), and nonvolatile memory devices, such as ROM (read only memory), according to how they lose their stored content when the power is cut off. The electrically erasable and programmable ROM (EEPROM) and flash memory are types of nonvolatile memories that are rewritable, except that rewriting is far more time-consuming than just reading. Thus, they typically are used as special-purpose memories where writing is seldom necessary. The flash memory is an advanced type of EEPROM, which may be electrically erased at high speed by using Fowler-Nordheim (F-N) tunneling and hot electrons, without being removed from the circuit board.
It is expected that the flash memory will someday replace the magnetic disk memory because of its various advantages, such as small cell size, quick access time, small power consumption, etc. The cost per bit of producing the flash memory, however, needs to be reduced per bit by decreasing the number of the processing steps required for its fabrication together with its cell size. Accordingly, the art has proposed the flash memory cell having a self-aligned shallow trench isolation (SA-STI) structure in order to reduce the size of the memory cell by forming the floating gate pattern in the same way as the active pattern for defining the active regions in a semiconductor substrate. Forming the respective patterns in this manner decreases the isolation distance between the adjacent bit lines.
The conventional flash memory cell having a SA-STI structure typically includes a stacked gate structure having a floating gate formed over a tunnel oxide layer for F-N tunneling, the tunnel oxide layer being formed in a silicon substrate with the active regions defined by STI. The stacked gate structure also contains a control gate formed over the floating gate with a dielectric interlayer formed therebetween. Data storage is achieved by applying a voltage between the control gate and the substrate to thereby inject or discharge electrons into or from the floating gate. In this case, the dielectric interlayer maintains the charged characteristics and transfers the voltage of the control gate to the floating gate. The amount of the voltage transferred from the control gate to the floating gate is proportional to the coupling coefficient “R” expressed by the following equation:   R  =            C      ONO                      C        ONO            +              C        TO            
Wherein CONO is the capacitance of the dielectric interlayer, and CTO is the capacitance of the tunnel oxide layer. In this case, because the capacitance “C” is expressed by the equation       C    =          ɛ      ⁢              A        T              ,wherein ε is the dielectric constant, and A and T respectively denote the area and thickness of the dielectric interlayer. The coupling coefficient may be increased either by increasing the area or decreasing the thickness.
It is very difficult, however, to form a thin thermal oxide layer over the floating gate composed of doped polysilicon. Because of this difficulty, as well as the increase of the leakage current, a composite oxide/nitride/oxide layer presently is used for the dielectric interlayer. In addition, the composite layer generally has a greater dielectric constant than the pure oxide layer thereby making its use more advantageous. Known methods of forming the composite layer include growing the first oxide layer by a thermal oxidation process, then depositing a nitride layer by a low-pressure chemical vapor deposition (LPCVD) process, and finally growing the second oxide layer by the thermal oxidation process. For example, fabricating a flash memory having a capacity on the order of about 256 Mb typically includes making the second doped polysilicon layer for the floating gate by oxidization to grow the first oxide layer to a thickness of about 100 Å, then depositing a nitride layer to a thickness of about 130 Å, and finally growing the second oxide layer to a thickness of about 40 Å again by oxidation, thereby obtaining the dielectric interlayer having an equivalent thickness of about 100 to about 200 Å.
The second oxide layer usually is formed to prevent pin holes from being generated in the nitride layer which is structurally not densified when compared to the oxide layer. This second oxide layer helps determine the insulating characteristics of the ONO dielectric layer. In addition, the second oxide layer may be grown to a thickness of about 1500 to about 2000 Å on a bare silicon substrate by wet oxidation. However, the nitride layer coated on the substrate may grow the oxide layer only up to a thickness of about 20 to about 70 Å. In order to form the second oxide layer to a thickness of about 1500 to about 2000 Å by wet oxidation, a high temperature process over 950° C. usually is employed. This high temperature process causes the polysilicon grains of the floating gate contacting the tunnel oxide layer to grow greatly so as to exert a stress to the tunnel oxide layer, thereby degrading it. This problem can be prevented if the second oxide layer is formed with a very thin thickness, but a thin second oxide layer increases the leakage current.
In addition, as the doping concentration of the polysilicon is increased, the thickness of the thermal oxide layer formed on the polysilicon is increased by oxidation enhancement, so that it is very difficult to control the thickness of the first oxide layer within a small value and make the layer thinner. For example, since it is expected that the thickness of the ONO dielectric layer would be about 110 to about 140 Å in a VLSI flash memory having a capacity on the order of 1 Giga-byte, the thermal oxidation is too limited for reducing the thickness to increase the coupling coefficient. Further, if the first oxide layer of the dielectric interlayer is formed over the floating gate by thermal oxidation, the reaction between oxygen and silicon is inadequately made in the corners of the floating gate that have less silicon lattices. Hence, the thickness of the first oxide layer becomes much thinner in the corners than in the side and upper parts, so that the electric field is concentrated in the corners which degrades the breakdown characteristics.